The present invention relates to a semiconductor memory device, and more particularly, to a flash memory device and a programming method for the flash memory device.
Semiconductor memories may be classified into random access memories (RAM) and read only memories (ROM). RAM is generally volatile in nature. That is, data stored in RAM is lost when power is interrupted. ROM is generally non-volatile in nature and retains stored data when power is interrupted. RAM includes the dynamic RAM (DRAM) and static RAM (SRAM). ROM includes the programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), and a flash memory. Flash memory may be further classified into NAND flash memory and NOR flash memory. NAND flash memory has a higher level of device integration relative to NOR flash memory.
FIG. 1 is a block diagram of a conventional flash memory device. Additional background information regarding conventional flash memory devices may be had by reviewing the subject mater of Korean Patent Publication No. 10-2006-0131507. Referring to FIG. 1, flash memory device 100 includes a memory cell array 110, a word line decoder 120, and a high voltage generator 130. The memory cell array 110 includes a plurality of memory blocks, each of which is connected to the word line decoder 120. Only one memory block and one word line decoder 120 are illustrated in FIG. 1, amongst the typical plurality of such elements included with flash memory devices.
The memory cell array 110 includes a plurality of memory strings CS respectively connected to “n” bit lines BL0 to BLn−1. The memory strings CS are connected to a common source line CSL. Gates of memory cells M0 to M15 of the memory strings CS are respectively connected to word lines WL0 to WL15. The gates of string selection transistors SST connecting the memory strings CS to the bit lines BL0 to BLn−1, respectively are connected to a string selection line SSL. The gates of ground selection transistors GST connecting each of the memory strings CS to the common source line CSL are connected to a ground selection line GSL.
The word line decoder 120 selectively activates the string selection line SSL, the ground selection line GSL, and the word lines WL0 to WL15 in the memory cell array 110. The word line decoder 120 includes a word line driver 124 receiving address signals (ADDR) and providing word line drive signals S0 to S15, a string selection voltage VSSL, and a ground selection voltage VGSL to the word lines WL0 to WL15, the string selection line SSL, and the ground selection line GSL, respectively.
The decoder 122 decodes the received address signals (ADDR) in order to provide corresponding drive voltages (e.g., a program voltage (Vpgm), an erase voltage Verase, a read voltage Vread, or a pass voltage Vpass) to the string selection line SSL, the word lines WL0 to WL15, and the ground selection line GSL during a program operation, an erase operation, or a read operation.
The word line driver 124 includes high voltage pass transistors SN, WN0 to WN15, GN, and CN, connected between the string selection voltage VSSL, the word line drive signals S0 to S15, the ground selection voltage VGSL, and the common source line voltage VCSL, and the string selection line SSL, the word lines WL0 to WL15, the ground selection line GSL, and the common source line CSL, respectively. A high voltage VPP generated from the high voltage generator 130 is connected to a block word line BLKWL to which the gates of the high voltage pass transistors SN, WN0 to WN15, GN, and CN are connected.
Once a pumping clock CLK_VPP is applied, the high voltage generator 130 generates a high voltage VPP during a charge pumping operation.
During a program operation of the flash memory device 100, to provide a program voltage to the word lines WL0 to WL15, the voltage difference between a high voltage and a program voltage should be greater than each threshold voltage of the high voltage pass transistors SN, WN0 to WN15, GN, and CN. However, if the voltage difference between a high voltage and a program voltage is too high, unnecessary power consumption occurs and the high voltage pass transistors SN, WN0 to WN15, GN, and CN may become damage by the overly high voltage. In contrast, if the voltage difference between a high voltage and a program voltage is too low, the high voltage pass transistors SN, WN0 to WN15, GN, and CN may not be turned ON, and the program voltage will not be provided to the word lines WL0 to WL15.
During a program operation performed by the flash memory device 100, the program voltage is typically increased by defined increments. The conventional flash memory device 100 controls the applied high voltage signal in order to maintain a level greater than the highest level of the program voltage (i.e., the value of the program voltage following its final increment). Unfortunately, because the high voltage signal is maintained at this level regardless of the program voltage actually used during a current program operation, unnecessary power consumption occurs and the high voltage pass transistors SN, WN0 to WN15, GN, and CN may become damaged by the unnecessarily elevated high voltage signal.